• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    A hierarchical unary/thermometer coder comprises a cascade of lower level coders that minimize clock loading and clock transitions by only enabling the clocking of a circuit when that circuit is required to change state, thereby minimizing power consumption. At the lowest level, a stage-1 circuit produces a two-bit unary/thermometer code using two NAND gates, an inverter, and a single set-reset latch. An output of the latch forms a least significant bit (LSB) and is used to control transitions of the next most significant bit. A stage-2 circuit produces a four-bit unary/thermometer code using two stage-1 circuits and a NOR gate. A stage-3 circuit produces an eight-bit unary/thermometer code using two stage-2 circuits and a NAND gate. The circuit associated with each higher order bit is only enabled when the next lower bit has been set. Outputs are also provided for generating a "running one" or "running zero" code.
    公开号:NL2021595A
    申请号:NL2021595
    申请日:2018-09-10
    公开日:2019-03-19
    发明作者:Johannes Karel Van Elzakker Michiel
    申请人:Semiconductor Ideas To The Market Itom B V；
    IPC主号:
    专利说明:


    Netherlands Patent Office © 2021595 © A PATENT APPLICATION © Application number: 2021595 © Int. Cl .:
    H03M 7/16 (2018.01) H03M 1/46 (2018.01) © Application submitted: September 10, 2018
    © Priority: © Applicant (s): September 15, 2017 US 62 / 559,293 Semiconductor Ideas to the Market (ITOM) November 9, 2017 US 15 / 808,863 B.V. in Eindhoven. © Application registered: © Inventor (s): March 19, 2019 Michiel Johannes Karel van Elzakkerin Eindhoven. © Request published:March 22, 2019 © Authorized representative:J. van Straaten in Uden.
    © HIERARCHICAL UNARY / THERMOMETER CODER FOR CONTROLLING AN ANALOG TO DIGITAL CONVERTER
    57) A hierarchical unary / thermometer coder comprises a cascade of lower level coders that minimize clock loading and clock transitions by only enabling the clocking of a circuit when that circuit is required to change state, minimize minimizing power consumption. At the lowest level, a stage-1 circuit produces a two-bit unary / thermometer code using two NAND gates, an inverter, and a single set-reset latch. An output of the latch forms a least significant bit (LSB) and is used to control transitions of the next most significant bit. A stage-2 circuit produces a four-bit unary / thermometer code using two stage-1 circuits and a NOR gate. Astage-3 circuit produces an eight-bit unary / thermometer code using two stage-2 circuits and a NAND gate. The circuit associated with each higher order bit is only enabled when the next lower bit has been set. Outputs are also provided for generating a running one or running zero code.
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    This publication corresponds to the documents originally submitted.
    HIERARCHICAL UNARY / THERMOMETER CODER FOR CONTROLLING AN ANALOG TO DIGITAL CONVERTER
    The present invention relates to a logic circuit for converting a digital clock signal to a unary / thermometer control signal.
    Unary coding, in some technical fields called thermometer code although there is often no link with thermometry as such, is an entropy encoding that represents a natural number, n, with n ones followed or preceded by a number of zeros (if natural number is understood as non-negative integer) or with n - 1 ones followed or preceded by a number of zeros (if natural number is understood as strictly positive integer). For example, 5 can be represented as 111110 or 11110 or 011111 or 01111. Some representations use n or n - 1 zeros followed or preceded by a numbers of ones. The ones and zeros are interchangeable without loss of generality.
    In particular the invention relates to a logic circuit forming a unary / thermometer coder for a digital controller for a low power successive approximation type or analog-to-digital converter (SAR ADC). However, the coder according to the present invention is also suitable for other low power digital applications, such as "Internet Of Things Devices", "Wireless Sensor Nodes", "Ultra Low Power Digital Signal Processor" and / or "Ultra Low Power digital circuits ”.
    SAR ADCs are circuits that include a sample-and-hold circuit for sampling an input signal, a comparator, for comparing the sample to the output or a digital to analog converter (DAC) and a controller, for controlling the DAC based on the comparison of the sample and the DAC output. In general, the controller may be configured for activating functional blocks in a specific order, which may, for a SAR ADC algorithm, include activating a sample-and-hold switch, activating a comparator, failure comparator results in a register, changing DAC values , making register contents available at an ADC output, or resetting internal register contents.
    The controller may thereto receive a digital clock signal that is converted by a coder to a signal that is suitable for use by the algorithm decoder or the controller. Such a signal may be in the form of a unary / thermometer signal (showing an increasing number of digital ones in a string or bits indicating a higher value), a running one or running zero signal (representing the position of a digital one or digital zero in a string indicates a value), or dual equivalents with numbers or positions of digital zeros.
    The conversion of a clock signal to one of the above signal forms is performed by logic circuitry, which are according to the state of the art, in particular circuits comprised of or digital flip flops. However, these state of the art solutions have the disadvantage that they consume a relatively high power, especially their dynamic supply current, i.e. a current required for state changes, is rather high and in most cases, it is dominant over the leakage current. This dynamic supply current increases with the ripple path, which is the number of electronic nodes that toggle in response to a clock or signal edge, the average capacitive load on these nodes, which depends on the number of digital gates that are driven, the frequency or operation, the supply voltage, and temperature and process parameters.
    United States Patent USP 6,310,653 discloses a unary / thermometer coder circuit.
    It is therefore a goal of the present invention to provide a logic circuit for converting a digital clock signal to a control signal that lacks the above mentioned disadvantages.
    The invention provides a unary / thermometer coding circuit for converting a digital clock signal to a control signal for an analog to digital converter, the circuit including:
    a first logic circuit that receives a first clock input and a first enable input and provides a first clocking signal;
    a set-reset latch that receives the first clocking signal as a set input, and a first reset input as a reset input and provides a first output; and a second logic circuit that receives the first clocking signal and the first latch output to provide a second output;
    in the first output and the second output form a two-bit unary / thermometer code based on the first clock input.
    A first improvement on the prior art is the use of logic gates, in particular NAND gates, NOR gates, and inverters. Herewith, the unary / thermometer coder avoids regular flip-flops during normal operation, which leads to a reduction of the dynamic supply current, since flip-flops have a larger internal number of digital gates that are driven. The topology itself takes away the need for a clock tree, and the lack of a long and wide ripple path, which is the number of electronic nodes that toggle in response to a clock or signal edge.
    In state of the art low power digital design, clock gating can be used to reduce the ripple path. Clock gating control signals are derived from the state of the flip-flops. In this new topology, the same gates are used to hold the digital output and to configure the internal multiplexing to propagate the next input clock only to where it is required.
    With respect to United States Patent USP 6,310,653 it is remarked that said prior art document does not disclose or suggest a unary / thermometer circuit including a first stage circuit including a first logic circuit that receives a first clock input and a first enable input and provides a first clocking signal, nor does it disclose or suggest a set reset latch that receives the first clocking signal as a set input, and a first reset input as a reset input and provides a first output, nor does it disclose or suggest a second logic circuit that receives the first clocking signal and the first latch output to provide a second output, nor does it disclose or suggest the first output and the second output forming a two-bit unary / thermometer code based on the first clock input ..
    Additionally, the coder according to the invention can be combined with a lower frequency or operation and a lower supply voltage to achieve lower power consumption over a certain range.
    As an option, standard flip-flops can be used to implement low-level testability. These only need to be active during test mode, when the device is powered from a tester without relevant power limitations.
    The logic circuit according to the invention in its simplest form (Fig. 4) provides a circuit SL1 for providing a unary / thermometer output Q1, Q0 passed on a clock signal C1. In this simplest form only two outputs are present, however, this circuit can be cascaded with similar or in particular, the same circuit to form an nstage unary / thermometer circuit.
    In order to enable building a circuit that outputs a running one, in an embodiment, the first clocking signal P may be made available as an output connection.
    In all cases, the circuit according to the invention reacts on both a positive and a negative clock edge C1. It is understood throughout this application that equivalent circuits to the ones presented and / or claimed to be part of the invention as well.
    In a further embodiment (Fig. 5), the invention comprises a second level assembly SL2 comprising two electronic circuits like the one described above, SL1A and SL1B, and including:
    a third logic circuit that receives a second clock input C2 and a second enable input E2 and provides a second clocking signal P2;
    a first instantiation of the first stage SL1B circuit that provides the first and second outputs QOB, Q1B; and a second instantiation of the first stage circuit SL1A that provides a third output and a fourth output QOA, Q1A;
    if:
    the second clocking signal P2 is coupled to the first clock input or the first and second instantiations or the first stage circuits;
    NOT (the second output) (QN1B) is coupled to the first enable input E1 or the first instantiation or the first stage circuit SL1B;
    a second reset input R2 is coupled to the first reset input R1 or the first instantiation or the first stage circuit SL1B;
    the second output Q1B is coupled to the first enable input E1 and the first reset input R1 or the second instantiation of the first stage circuit SL1A; and the first, second, third, and fourth outputs QOB, Q1B, QOA, Q1A form a fourbit unary / thermometer code based on the second clock input, QOB being the least significant bit.
    Also for the assembly of the second stage circuit, in an embodiment, the clocking signal P of the first logic NAND gates of the respective circuits SL1 A, SL1B may be made available as output connections PA, PB for creating a running one, or running zero circuit.
    The circuit according to the invention may be cascaded multiple times. Every next level is formed by combining two assemblies from the previous level, alternatingly combined with a logic NOR or a logic NAND gate for forming the corresponding clocking signal, as detailed further below.
    The invention will now be presented in more detail with reference to the following figures. Herein:
    Figure 1 shows an overview of a SAR ADC with a controller that includes a unary / thermometer coder in accordance with this invention;
    Figure 2 illustrates a unary / thermometer coding or (binary) numbers; Figures 3a-e show coder outputs after various numbers or clock edges;
    Figure 4 shows an electronic circuit according to the invention;
    Figure 5 shows a hierarchical unary / thermometer coder comprising two electronic circuits from Figure 4;
    Figure 6 shows a hierarchical unary / thermometer coder comprising two assemblies from figure 5.
    Figure 1 shows an overview of a Successive Approximation Type or Analog Digital converter. The first step of the Successful Approximation algorithm is for the Sample / Hold circuit to generate a Sampled input. The Register initialized the DigitalAnalog-Converter at its initial center Successful Approximation value (MSB set; all other bits clear). The Comparator compares the signals from Digital-Analog Converter (DAC) and Sample / Hold. The Comparison result is fed to the Register, which uses it to adjust the Successive Approximation value towards the Sampled Input by setting or clearing the MSB, based on whether the sampled input is greater than or less than the signal from the DAC, respectively. These steps are then repeated for the next less significant bit until the Comparator has executed N comparisons for an N-bit conversion. Afterwards the Digital Output is made available and the algorithm restarts. This highly repeatable algorithm is controlled from a Successive Approximation Algorithm Decoder, the output of which is a combinational function of the unary / thermometer signal received from the unary / thermometer coder.
    Figure 2 shows a table explaining a unary / thermometer coding or binary numbers, which may be one example of the output, provided by the coder inside the Controller from figure 1. As used read, the terms zero and one, or 0 and 1, indicate the pair of values that a binary signal may have; as is well known in the art, the current voltages assigned to each value is arbitrary, provided that the two voltages are distinguishable, and that the logic devices perform appropriately with these voltages. In logic terms, zero and one may correspond to false and true respectively.
    Figures 3a-e show coder outputs after various numbers or clock edges. It is apparent that the output is a unary / thermometer-type code or which the number of ones increases.
    Figure 4 shows a stage 1 electronic circuit SL1 according to the invention. The circuit comprises a first NAND gate, having two inputs C1, E1 and an output P, a second NAND gate, having two inputs P, Q0 and an output QN1, an inverter having an input QN1 and an output Q1, a set-reset (SR) latch including mutually coupled third and fourth NAND gates, the latch having a set input, a reset input R1, a positive state output Q0 and a negative state output QNO. The clock C1, enable E1, and reset R1 inputs are made available as input connections.
    The pulse-like output P of the first NAND gate serves as a clocking signal that is enabled when signal E1 is one, and is coupled to a first input of the second NAND gate and to the set input of the SR latch. A positive state output Q0 or the SR latch is coupled to the second input or the second NAND gate. A negative state output QN1 or the second NAND gate is coupled to the input of the inverter and the output of the inverter is made available as a positive state output Q1 connection.
    The outputs Q1, Q0 form a two-bit unary / thermometer code, with Q1 as the most significant bit (MSB), and Q0 as the least significant bit (LSB). The Q0 and Q1 outputs are reset to zero when R1 and E1 are set to zero. The circuit is enabled when R1 and E1 are set to one.
    Before E1 is set to one, the output P of the first NAND gate will be hero at one, which will have no effect on the second NAND gate, because Q0 has been reset to zero, and it will have no effect on the SR latch because only a zero input will change the state of the latch after it has been reset. After E1 is set to one, the output P will be the inverse or the clock signal C1. Preferably, E1 is set to one when the clock input C1 is at zero, to hold P at one until the next transition of the clock input C1.
    When C1 goes to one, P will be set to zero, which will cause the SR latch to be set, changing Q0 to one. P being at zero will also force the second NAND gate to remain set to one, keeping Q1 set to zero.
    When C1 next goes to zero, P will be set to one, which will force the second NAND gate to go, changing Q1 to one. The transition from P to one will have no effect on the SR latch, keeping Q0 set to one. Thus, the two-bit output for the above sequence will be: 00, 01, 11.
    It is significant to note that the output Q0 or the SR latch is used to hold the state of the LSB, as well as to control the enabling of the second NAND gate to set the output Q1 on the next transition of the clock signal C1 from one to zero.
    As an option, in order to enable building a circuit that outputs a running one, or a running zero, the output P or the first NAND gate may be made available as an output connection. As a further option, in order to be able to output a negative unary / thermometer, the output QN1 or the second NAND gate and a negative state output QN0 or the latch may be available as output connections.
    One of skill in the art will recognize that equivalent (dual) circuit elements may be used in lieu of the devices illustrated. For example, at the lowest level, the cross-coupled NAND gates or the set-reset latch could be replaced by a pair or cross-coupled NOR gates (with appropriate polarity inversions to the set and reset inputs). In like manner, a NAND gate can be replaced by an OR gate with inverted inputs, and a NOR gate can be replaced by an AND gate with inverted inputs.
    Figure 5 shows a stage 2 assembly of SL2 or two electronic circuits from Figure 4, which are referred to here as SL1A and SL1B, and a NOR gate. The two inputs, clock C2 and enable E2, or the NOR gate are made available as input connections; and the output from the NOR gate, which serves as a second stage clocking signal that is enabled when E2 is zero, is coupled to the clock inputs C1 or both electronic circuits SL1 A, SL1B. The positive state output of the first electronic circuit Q1B is coupled to the enable E1 and reset R1 inputs of the second electronic circuit SL1A and the negative state output QN1B of the first electronic circuit SL1B is coupled to the enable input E1 or the first electronic circuit SL1B.
    It is significant to note that the stages SL1A and SL1B are selectively enabled, and that SL1A will not be enabled until after the MSB Q1B or SL1B is set to one; this signal Q1B also maintains SL1A in a reset state until Q1B is set to one. The inverse of this signal QN1B also removes the enable signal E1 from SL1B, such that it retains its current state. That is, SL1A is not enabled until it is needed to change state, and SL1B is disabled after it reaches its maximum state, avoid minimizing transient power consumption. Also note that the input clock signal C2 is only coupled to one logic gate, which minimizes the loading (fanout) on the clock signal.
    The outputs Q1A, QOA, Q1B, QOB or the two electronic circuits SL1A, SL1B are made available as positive state output connections, creating a four-bit unary / thermometer coding, with Q1A as the MSB, and QOB as the LSB. The reset input R1 or the second electronic circuit SL1B is made available as a reset input connection R2, which will reset all the positive Q outputs to zero when it is zero. When enabled, this stage-2 assembly will produce the following sequence of outputs: 0000, 0001, 0011, 0111, 1111.
    Optionally, in an embodiment, the pulse outputs P or the respective circuits SL1 A, SL1B may be made available as output connections PA, PB, for creating a running one, or running zero circuit, and the outputs QN1A, QN0A, QN1B, QN0B of the electronic circuits SL1 A, SL1B may be made available as negative state output connections, in order to provide an inverse unary / thermometer output.
    Figure 6 shows a stage-3 assembly or two assemblies from figure 5, forming a third-stage or the unary / thermometer coder. This third level assembly SL3 comprises two second level assemblies SL2A, SL2B as described above with reference to figure 5, and a NAND gate, C3 and enable E3 inputs or the NAND gate are made available as input connections; and the output of the NAND gate form a third-stage clocking signal P3 and is coupled to the inputs C2 or both electronic circuits SL2A, SL2B.
    The positive state output Q1 AB or the first second level assembly SL2B is coupled to the reset input R2 or the second second level assembly SL2A and to the enable input E2 or the first second level assembly SL2B. A negative state output of the first electronic circuit QN1AB is coupled to the enable input E2 or the second second level assembly SL2A.
    As in the second stage or FIG. 5, it is significant to note that the stages SL2A and SL2B are selectively enabled, and that SL2A will not be enabled until after the MSB Q1 AB or SL2B is set to one (QN1 AB set to zero). Also note that after Q1 AB is set to one, SL2B is not enabled, and will retain its current state. That is, SL2A is not enabled until it is needed to change state, and SL2B is not enabled once it reaches its maximum state (Q1AB and QOAB set to one), avoid minimizing transient power consumption. Also as in FIG. 5, the clock signal C3 is only coupled to one logic gate, expect minimizing its loading (fanout).
    The outputs Q1AA, QOAA, Q1BA, QOBA, Q1AB, QOAB, Q1BB, QOBB or the two second level assemblies SL2A, SL2B are made available as positive output connections, and form an 8-bit unary / thermometer coding, with Q1AA as the MSB , and QOBB as the LSB.
    For ease of illustration, the optional P signals from the second level assemblies are not shown. However, if a moving one output is required, the PA and PB outputs or the respective circuits SL2A, SL2B may be made available as output connections. The outputs QNOAA, QN1AA, QNOBA, QN1BA, QNOAB, QN1AB, QNOBB, QN1BB or the electronic circuits SL2A, SL2B may be available as negative state output connections for creating an inverse unary / thermometer signal.
    The output of this 8-bit unary / thermometer coder can be used by a Successive Approximation Algorithm Decoder to control the other parts of the analog-to-digital converter, as indicated in Figure 1, with C3, E3, and R3 serving as the clock, enable, and reset inputs. In this embodiment, the coder is reset to zero when E3 and R3 are zero, and enabled when E3 and R3 are at one. When enabled, each transition or the clock signal C3 (both rising and falling) will cause a subsequent Q output to be set to one. The output can serve, for example, to indicate which bits of the Successive Approximation Algorithm Decoder have been processed.
    It is significant to note that at stage 1, a NAND gate was used to provide the clocking signal, at stage 2, a NOR gate was used, and at stage 3, a NAND gate was used. This alternating NAND-NOR arrangement will be repeated with each additional stage. That is, for example, a four-stage coder (16-bit) would use a NOR gate, a five-stage coder (32-bit) would use a NAND gate, etc.
    One of skill in the art will recognize that when a number of n cascaded stages are insufficient, but n + 1 stages are more than required, an intermediate implementation can be made using only enough SLs as needed, with suitably staging. That is, if a 12-bit unary / thermometer coder is required, it could be formed using one SL3 (8-bit) and one SL2 (4-bit).
    The examples given above are exemplary only and serve in no way to limit the scope of protection as defined in the following claims.
    In the following claims, the logic terms of NOT, AND, NAND, OR, and NOR (capitalized) are interpreted in their standard form. NOT (zero) is one; NOT (one) is zero. AND is one only when all of its arguments are one. NAND is zero only when all of its arguments are one. OR is one when any of its arguments are one. NOR is zero when any of its arguments are one.
    In interpreting these claims, it should be understood that:
    a) the word includes does not exclude the presence of other elements or acts than those listed in a given claim;
    b) the word or an preceding element does not exclude the presence of a variety of such elements;
    c) any reference signs in the claims do not limit their scope;
    d) any of the disclosed devices or portions of may be combined together or separated into further portions unless specifically stated otherwise;
    e) the term multiple of an element includes two or more of the claimed element, and does not imply any particular range or number of elements; that is, a variety of elements can be as few as two elements, and can include an immeasurable number of elements.
    The invention also relates to a computer chip including a circuit and / or a converter. It also relates to an electronic device including such a chip.
    权利要求:
    Claims (17)
    [1]
    Conclusions
    1. Unair / thermometer coding circuit comprising:
    a first level circuit (SL1) including a first logic circuit adapted to receive a first clock input (C1) and a first enable input (E1) and to provide a first clock signal (P);
    a set reset latch (SR Latch) capable of receiving the first clock signal (P) as a set input (set) and a first reset input (R1) as a reset input (reset) and for providing a first output (Q0); and a second logic circuit adapted to receive the first clock signal (P) and the first output (Q0) for providing a second output (Q1);
    in which:
    the first output (Q0) and the second output (Q1) form a two-bit union / thermometer code based on the first clock input (C1).
    [2]
    The circuit of claim 1 wherein:
    the first clock signal (P) is equivalent to NOT (the first clock input C1) AND the first enable input (E1)):
    the second output (Q1) is equivalent to the first clock signal (P) AND the first output (Q0).
    [3]
    The circuit of claim 1 wherein:
    the first clock signal (P) is equivalent to NOT (the first clock input C1) OR the first enable input (E1)):
    the second output (Q1) is equivalent to the first clock signal (P) OR the first output (Q0).
    [4]
    4. A circuit according to any one of the preceding claims, wherein the first logic circuit forms a combinatorial, non-sequential, logic circuit.
    [5]
    Circuit according to one of the preceding claims, wherein the set-reset latch contains cross-linked NAND ports.
    [6]
    Circuit according to one of claims 1 to 4, wherein the set-reset latch contains cross-linked NOR gates.
    [7]
    Circuit according to one of the preceding claims, comprising:
    a second level circuit comprising:
    a third logic circuit adapted to receive a second clock input (C2) and a second enable input (E2) and to provide a second clock signal (P2);
    a first embodiment of the first logic circuit (SL1B) for providing the first (QOB) and the second output (Q1B) a second embodiment of the first logic circuit (SL1A) for providing a third (QOA) and a fourth output (Q1A) where:
    the second clock signal (P2) is coupled to the first clock inputs (C1) of the first embodiment (SL1B) and second embodiment (SL1A) of the first level circuits;
    NOT (the second output) (QN1B) is coupled to the first enable input (E1) of the first embodiment of the first level circuit (SL1B), a second reset input (R2) is coupled to the first reset input (R1) of the first embodiment of the first level circuit (SL1B);
    the second output (Q1B) is coupled to the first enable input (E1) and the first reset input (R1) of the second embodiment of the first level circuit (SL1A); and the first, second, third, and fourth outputs (QOB, Q1B, QOA, Q1A) form a four-bit unary / thermometer code based on the second clock input (C2).
    [8]
    The circuit of claim 7 wherein:
    the second clock signal (P2) is equivalent to NOT (the second clock input C2) AND the second enable input (E2)).
    [9]
    The circuit of claim 7 wherein:
    the second clock signal (P2) is equivalent to NOT (the second clock input C2) OR the second enable input (E2)).
    [10]
    The circuit of any one of claims 7 to 9, including a third level circuit including a fourth logic circuit capable of receiving a third clock input (C3) and a third enable input (E3) and providing a third clock signal (P3);
    a first embodiment of the second level circuit (SL2B) for providing the first, second, third and fourth output (QOBB, Q1 BB, QOAB, Q1AB) a second embodiment of the second level circuit (SL2A) for providing a fifth, sixth, seventh and eighth output (QOBA, Q1BA, QOAA, Q1AA) in which:
    the third clock signal (P3) is coupled to the second clock input (C2) of the first (SL2B) and second (SL2A) versions of the second level circuit;
    the fourth output (Q1AB) is coupled to the second enable input (E2) of the first embodiment of the second level circuit (SL2B) and to the second reset input (R2) of the second embodiment of the second level circuit (SL2A);
    NOT (the fourth output) (QN1AB is coupled to the second enable input (E2) of the second embodiment of the second level circuit (SL2A);
    a third reset input (R3) is coupled to the second reset input (R2) of the first embodiment of the second level circuit (SL2B); and the first, second, third, fourth, fifth, sixth, seventh and eighth outputs (QOBB, Q1BB, QOAB, Q1AB, QOBA, Q1BA, QOAA, Q1AA) form an eight-bit unary / thermometer code based on the third clock input (C3).
    [11]
    The circuit of claim 10, wherein the third clock signal (P3) is equivalent to NOT (the third clock input (C3) AND the third enable input (E3)).
    [12]
    The circuit of claim 10, wherein the third clock signal (P3) is equivalent to NOT (the third clock input (C3) OR the third enable input (E3)).
    [13]
    The circuit of claim 10 wherein the first, second, and third level circuits are also configured to provide a "running one" or "running zero" output sequence.
    [14]
    14. An analog-to-digital converter comprising:
    a control circuit including a union / thermometer encoder for providing an output according to a union / thermometer code based on a clock input;
    a successive approximation algorithm decoding circuit for selecting the bit position to be analyzed based on the output according to a union / thermometer code;
    a register circuit for providing a digital output that forms a successive approach to a sampled analog signal;
    a digital-to-analog converter circuit for converting the digital output to an analog reference value;
    a sample / hold circuit for receiving an analog input signal and providing a sampled analog signal;
    a comparator for comparing the analog reference value and the sampled analog signal to provide a binary comparison result;
    wherein the register circuit uses the binary comparison result to provide a subsequent successive approximation result;
    wherein the union / thermometer encoder contains a plurality of levels, wherein each level comprises one or more first level circuits, the circuits comprising:
    a first logic circuit adapted to receive a first clock input (C1) and a first enable input (E1) and to provide a first clock signal (P);
    a set reset latch (SR Latch) capable of receiving the first clock signal (P) as a set input (set) and a first reset input (R1) as a reset input (R1) and for providing a first output (Q0); and a second logic circuit adapted to receive the first clock signal (P) and the first output (QO) for providing a second output (Q1);
    in which:
    5 the first output (QO) and the second output (Q1) form a two-bit union / thermometer code based on the first clock input (C1).
    [15]
    The transducer of claim 14, wherein the union / thermometer encoder includes two pairs of second level circuits, wherein each second level
    The circuit comprises two first level circuits and the output according to a union / thermometer code corresponds to an eight-bit output according to a union / thermometer code.
    [16]
    A computer chip comprising a circuit according to any of claims 1 to 15 and to 13 and / or a converter according to any of claims 14-15.
    [17]
    An electronic device comprising a computer chip according to claim 16.
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    同族专利:
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US201762559293P| true| 2017-09-15|2017-09-15|
    US15/808,863|US10128867B1|2017-09-15|2017-11-09|Hierarchical unary/thermometer coder for controlling an analog to digital converter|
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